1. The Technical Field
The invention relates generally to electrical fault protection systems and, more particularly, to electrical fault protection systems providing for communication of information among the system""s protective devices.
2. The Prior Art
Fault protection systems (FPS""s) for protecting electrical power distribution systems (PDS""s) and components thereof have long been known in the art. A properly designed FPS isolates faults without unnecessarily isolating functional portions of the PDS.
Known FPS""s typically use protective devices such as circuit breakers and fuses to isolate faults. Conventional circuit breakers and fuses are limited in their ability to precisely locate and isolate faults. Such devices typically are designed to trip based on predetermined time-current characteristics. That is, they are designed to trip after having passed a predetermined amount of excess current for a predetermined time. They are not designed to precisely identify fault locations.
Despite the limitations of conventional circuit breakers and the like, FPS""s using them can be designed so that, under many fault scenarios, the protective device immediately upstream of a fault will trip prior to protective devices farther upstream. Under ideal circumstances, a properly coordinated FPS can isolate faults with minimal disruption to unfaulted portions of the PDS.
However, under certain fault scenarios, conventional protective devices immediately upstream of a particular fault might not trip prior to conventional protective devices farther upstream. Under such scenarios, undamaged portions of the PDS might be unnecessarily isolated. Accordingly, FPS""s using conventional circuit breakers have limited ability to isolate faults precisely without undue disruption to unfaulted portions of the PDS, particularly where the FPS comprises a power grid network where a particular protective device may be either upstream or downstream of another protective device, depending on the configuration of the power grid network.
Some prior art protective devices monitor current direction and incorporate trip logic which considers current direction, as well as current magnitude, through the device. These devices can be used to isolate faults somewhat more precisely than other conventional protective devices. However, they are also limited in their ability to isolate faults without unnecessarily isolating unfaulted portions of the systems.
One known FPS comprises current monitors and protective switching devices which are located at strategic points about the PDS. The FPS further comprises a microprocessor and a communications network through which the microprocessor communicates with each of the current monitors and protective switching devices. When the microprocessor""s analysis of data it receives from one or more of the current monitors indicates the presence of a faulted condition, the microprocessor selectively transmits trip signals to those protective devices which the microprocessor perceives can most effectively isolate the fault without unduly isolating unfaulted portions of the PDS. Given a sufficient number of monitoring points and protective devices, this FPS can identify and isolate faults with a great degree of precision. However, the communications network used by this FPS is relatively complicated. Consequently, the FPS is not easily adapted to changes in the PDS architecture.
The foregoing system""s complexity lies in part in the manner in which the microprocessor recognizes inputs from the various current monitors and protective devices about the PDS. Each current monitor and protective device comprising the FPS is assigned a unique address through which it communicates with the microprocessor, i.e., the microprocessor recognizes the current monitors and protective devices by their addresses, not their actual physical locations. Therefore, it is critical that the current monitor and protective device addresses are accurately programmed so that the devices"" addresses are accurately correlated to the devices"" actual physical locations within the PDS. If any such addresses are not accurately programmed, the FPS is likely to respond to a fault on the PDS incorrectly. That is, the FPS may fail to isolate a fault, or it may inappropriately isolate an unfaulted portion of the PDS.
Ensuring that the current monitor and protective switching device addresses are properly correlated to their installed locations can be a complicated task, and one which must be executed each time the PDS is expanded or otherwise modified. Large portions of the PDS may need to be taken out of service while testing the system to verify that the addressing is correct. Such testing can be complicated and time consuming, and may require disruption to portions of the PDS which otherwise are not directly affected by the modifications.
Given its limitations, the foregoing FPS is best-suited for applications wherein the PDS configuration, once designed and constructed, is substantially fixed and not subject to revision. An example of such a system is the PDS for a ship. The foregoing FPS is not well-suited for use with a PDS which is subject to frequent modification or expansion or which cannot practically be taken out of service for modification or testing. Examples of such systems can include the PDS""s associated with commercial buildings and industrial facilities.
The invention is an advanced fault protection system that identifies the locations of faults in a power distribution system with a high degree of precision and causes such faults to be isolated quickly, without unnecessarily isolating or disrupting service to unfaulted portions of the PDS.
The FPS according to a preferred embodiment of the present invention identifies fault locations by monitoring power flow into and out of each power feed at each node in the PDS. In alternate embodiments, power flow can be monitored at fewer than all of the power feeds and/or nodes in the PDS. However, the greater the proportion of power feeds and/or nodes where power flow is monitored, the greater the FPS"" ability to precisely identify and isolate faults.
In a preferred embodiment, one or more power feeds connect each node in the PDS to other nodes. A circuit interrupter, such as a circuit breaker, load break switch, or other device capable of interrupting power in response to a trip signal, is located near each end of each power feed, near the node at that end of the power feed. A power monitor associated with each circuit interrupter monitors the magnitude and/or direction of power flowing through a monitoring point in the conductor and generates a signal indicative thereof. The power monitor may be integral to the circuit interrupter, or it may be a separate unit. In a preferred embodiment, each power monitor""s monitoring point is proximate the power monitor""s associated circuit interrupter. In some embodiments, it may be desirable to use current monitors instead of power monitors and to monitor current instead of power, as would be known to one skilled in the art.
A communications channel is provided whereby the signal generated by each power monitor is communicated to trip logic associated with its corresponding circuit interrupter and to trip logic associated with its complementary circuit interrupter, i.e., the circuit interrupter at the opposite end of the power feed. The trip logic associated with each circuit interrupter thus receives signals indicative of the magnitude and/or direction of power detected by its corresponding power monitor and the magnitude and/or direction of power detected by its complementary power monitor. In one embodiment of the invention, the communications channel is a hardwired communications line. In an alternate embodiment, the communications channel is a wireless communications channel.
The trip logic associated with each circuit interrupter is designed to recognize a faulted condition between its corresponding power monitor and its complementary power monitor when the signals it receives therefrom indicate that power is flowing in one direction past its corresponding power monitor and in the opposite direction past its complementary power monitor and/or that the power flowing past its corresponding power monitor is of substantially different magnitude than the power flowing past its complementary power monitor. In a preferred embodiment, where each power monitor senses power proximate its associated circuit interrupter, a fault located between a pair of complementary power monitors will also be located between the circuit interrupters associated with those power monitors.
Power flowing through each end of an unfaulted power feed has the same direction and substantially the same magnitude. Under such circumstances, based on the signals it receives from its corresponding and complementary power monitors, the trip logic associated with the circuit interrupter at each end of the power feed determines that no fault exists between its corresponding and complementary circuit interrupters, no trip signals are generated, and neither of the pair of complementary circuit interrupters changes state to an open state.
Power flowing through the first end of a faulted power feed has a different magnitude and/or direction than power flowing through the opposite end of the power feed. Under such circumstances, based on the signals it receives from its corresponding and complementary power monitors, the trip logic associated with the circuit interrupter at each end of the power feed recognizes that a fault exists between its corresponding and complementary circuit interrupters. Accordingly, the trip logic associated with the circuit interrupter at each end of the faulted power feed provides a trip signal to its associated circuit interrupter, causing its associated circuit interrupter to trip open. In this manner, the circuit interrupters at both ends of a faulted power feed trip open to isolate the power feed and the fault from the rest of the PDS.
The FPS can also be configured to identify faults on the node side of any of the circuit interrupters. In one such embodiment, the trip logic associated with each of the circuit interrupters at each end of a power feed is designed to recognize a faulted condition at a particular node when the power monitor associated with the circuit interrupter at that particular node fails to communicate a signal to its complementary circuit interrupter""s trip logic and when fault current is flowing through the complementary circuit interrupter towards the particular node. That situation indicates potential physical damage to the power monitor and/or circuit interrupter at the particular node which is likely to be the result of a fault at that node. In that situation, the complementary circuit interrupter is caused to trip open. On the other hand, the situation where the power monitor associated with the circuit interrupter at that particular node fails to communicate a signal to its complementary circuit interrupter""s trip logic but no fault current is flowing through the complementary circuit interrupter towards the particular node is indicative of the failure of the power monitor at the particular node or of a failed communications line; it is not indicative of a fault. Accordingly, in this situation, neither of the circuit interrupters at opposite ends of the power feed is caused to trip open.
In an alternate embodiment, communications are also established between each of the power monitors and the trip logic associated with each of the circuit interrupters located at each node. Should a fault occur at a node, i.e., on the node side of the circuit interrupters adjacent the node, the trip logic associated with each of those circuit interrupters determines that the amount of power entering the node exceeds the amount of power exiting the node, based on the signals the trip logic associated with each of those circuit interrupters receives from the several power monitors. Accordingly, the trip logic associated with each of those circuit interrupters recognizes a node-side fault and provides a trip signal to its associated circuit interrupter. Each of the circuit interrupters adjacent the faulted node then trips, thus isolating the node with minimal impact on the unaffected portions of the PDS.
Any or all of the circuit interrupters comprising the FPS may further incorporate conventional trip logic which will cause the circuit interrupters to trip in the presence of certain overcurrent conditions, and/or in the event that other portions of the advanced fault protection system of the present invention fail to operate as designed.